AI Patent Eligibility: 35 U.S.C. 101 Subject Matter Guidance and Alice/Mayo Rejection Defense

## Navigating Subject Matter Eligibility for Machine Learning Inventions

Prosecuting artificial intelligence and neural network patents requires overcoming the USPTO's two-step Alice/Mayo framework. Under 35 U.S.C. § 101, claims directed purely to mathematical algorithms, mental processes, or abstract data manipulation are subject to summary rejection unless anchored to specific technological improvements.

### 1. The USPTO AI Eligibility Decision Tree

| Examination Stage | Evaluation Question | Qualifying Evidence | Risk Factor |
|:------------------|:--------------------|:-------------------|:------------|
| Step 1 | Is the claim a statutory category (process, machine, manufacture)? | Method or apparatus claim format | Naked software code |
| Step 2A (Prong 1) | Does the claim recite an abstract idea (mathematical concept)? | Algorithmic formulas, linear algebra operations | Unapplied statistical equations |
| Step 2A (Prong 2) | Is the abstract idea integrated into a practical application? | Specific sensor integration, memory bus optimization | Generic computer invocation ('run on server') |
| Step 2B | Does the claim contain an inventive concept ('significantly more')? | Non-conventional pipeline arrangement, reduced parameter drift | Well-understood, routine, conventional steps |

### 2. Drafting Claims that Improve Computer Functionality

To establish eligibility under Federal Circuit precedent (*Enfish*, *Berkheimer*), claims must emphasize concrete technical improvements over baseline computational systems rather than commercial benefits:

```text
Claim 1 (Exemplary Structure):
A computing system for low-precision tensor operations comprising:
a hardware matrix-multiplication accelerator; and
a non-transitory memory storing instructions that, when executed, cause the accelerator to:
quantize a weight tensor into non-uniform 4-bit floating point representations;
execute channel-wise dynamic scale factor adjustment without dequantizing to 32-bit registers;
wherein the channel-wise dynamic adjustment reduces memory bus bandwidth by at least 45%.
```